Poseidon.
King of the silicon sea. The Sovereign AI SoC that runs the 25 brains on operator-personalised hardware.
Poseidon is the silicon-bound substrate beneath the Mickai cooperative. Where the Chronus subsystem conducts the cognitive mechanics that move work between brains, and the 25 domain brains carry the subject-matter expertise, Poseidon is the floor they stand on: an operator-personalised AI accelerator chip that binds the SIOS bundle to silicon, attests the host before any brain executes, migrates the audit chain when the SIOS moves across hosts, and bootstraps the distribution endpoint under operator control. The Sovereign AI SoC product line (patents 53, 54, 55, 57) opens at a £1,500 to £3,000 retail price point. Five inversions distinguish Poseidon from prior secure-enclave designs: operator-as-root-of-trust, host attesting to the silicon, SIOS bundle resident on the chip, audit chain that persists across hosts, and operator-controlled distribution endpoint.
- 01Bind the SIOS bundle to operator-personalised silicon at manufacture
- 02Attest host integrity to the silicon before any brain executes
- 03Migrate the audit chain across hosts without loss of lineage (patent 55)
- 04Bootstrap distribution under an operator-controlled endpoint (patent 57)
- 05Run the 25 specialist domain brains on hardware the operator owns
Authoritative external corpora and standards this brain treats as canonical. Every retrieval against these sources is signed into the audit ledger so a regulator can prove which evidence drove which output.
- 01Mickai Patents 53, 54, 55, 57
- 02RISC-V Instruction Set Architecture specification
- 03ARMv9-A Architecture Reference Manual
- 04TSMC process-node design rules
- 05IEEE 1500 and 1149.1 test-access standards
- 06NIST Cryptographic Module Validation Program (FIPS 140-3)
- 07Common Criteria EAL evaluation framework
- 08ITRS 2.0 semiconductor roadmap
- 09DARPA POSH open-source hardware reference
- 10TPM 2.0 specification
Mickai-native tooling primitives this brain implements internally. Codex for sovereign plain-text graph PKM, Lectern for spaced-repetition memory, Stele for citation-provenance, and domain-native primitives layered on top. No external services in the trust path; data stays on operator-personalised hardware.
- 01Crucible (silicon EDA and chip-design surface)
- 02Cipher (silicon-bound key custody)
- 03Threshold (host-attestation identity)
- 04Wax-Seal (manufacture-binding signing)
- 05Concord (audit-chain migration consensus)